ICS844020-45 Datasheet, PDF (9/13 Pages) Integrated Device Technology – FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER

ICS844020-45
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half.
This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω.
VDD
VDD
R1
Ro
Rs
.1uf
Zo = 50
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should
be no trace attached.
LVDS OUTPUT
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there
should be no trace attached.
IDT^™ / ICS^™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
9
ICS844020-45 REV A JUNE 14, 2006