ICS840271I Datasheet, PDF (9/13 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Schematic Example
Figure 4 shows an example of ICS840271I applications schematic.
In this example, the device is operated at V_DD = 3.3V. The input is
driven by either a 3.3V LVPECL or LVDS driver. One example of
LVCMOS termination is shown in this schematic. The decoupling
capacitors should be located a close as possible to the power pin.
Logic Input Pin Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD R1
10
VDDA
C2
0.1u
C3
10u
SEL0
VDD
R3
R4
125
125
U1
1
2
3
VDDA
SEL0
4
CLK
nCLK
LVPECL Driv er
Zo = 50
Zo = 50
CLK
nCLK
R5
R6
84
84
Figure 4. ICS840271I Schematic layout
VDD
C1
0.01u
VDD
Q
8
7
6
GND
SEL1
5
Q
SEL1
R2
33 Zo = 50 Ohm
LVCMOS
IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
9
ICS840271BGI REV. A APRIL 23, 2009