ICS840271I Datasheet, PDF (10/13 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS840271I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS840271I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)_MAX = V_{DD_MAX} * (I_DD + I_DDA) = 3.465V *(75mA + 8mA) = 287.6mW
• Output Impedance R_OUT Power Dissipation due to Loading 50Ω to V_DD/2
Output Current I_OUT = V_{DD_MAX} / [2 * (50Ω + R_OUT)] = 3.465V / [2 * (50Ω + 16Ω)] = 26.25mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (R_OUT) = R_OUT * (I_OUT)² = 16Ω * (26.25mA)² = 11mW per output
Total Power Dissipation
• Total Power
= Power (core)_MAX + Total Power (R_OUT)
= 287.6mW + 11mW
= 298.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.299W *129.5°C/W = 123.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 6. Thermal Resistance θ_JA for 8 Lead TSSOP, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
1
125.5°C/W
2.5
123.5°C/W
IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
10
ICS840271BGI REV. A APRIL 23, 2009