ICS840271I Datasheet, PDF (2/13 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Table 1. Pin Descriptions
Number
1
2
Name
V_DDA
SEL0
Type
Power
Input Pulldown
Description
Analog supply pin.
Selects the input reference frequency and the PLL bypass mode.
LVCMOS/LVTTL interface levels. See Table 3.
3
CLK
Input Pulldown Non-inverting differential clock input.
4
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to V_DD/2.
5
SEL1
Input
Pullup
Selects the input reference frequency and the PLL bypass mode.
LVCMOS/LVTTL interface levels. See Table 3.
6
GND
Power
Power supply ground.
7
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
8
V_DD
Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter
C_IN
Input Capacitance
R_PULLUP Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance
Test Conditions
V_DD = 3.465V
V_DD = 2.625V
Minimum
Typical
4
51
51
16
19
Maximum
Units
pF
kΩ
kΩ
Ω
Ω
Function Tables
Table 3. SEL[1:0] Function Table
Inputs
SEL1
SEL0
CLK, nCLK (MHz)
0
0
REF
0
1
161.1328125
1 (default)
0 (default)
156.25
1
1
125
NOTE: REF = Input clock signal frequency
Mode
PLL Bypass
PLL Enabled
PLL Enabled
PLL Enabled
Output (MHz)
REF/ 5
25
25
25
IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
2
ICS840271BGI REV. A APRIL 23, 2009