ICS8312 Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER

ICS8312
LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
Table 5E. AC Characteristics, V_DD = 3.3V ± 5%, V_DDO = 1.8V ± 0.2V, T_A = 0°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tjit
Output Frequency
200
MHz
Propagation Delay, Low to High; NOTE 1
ƒ ≤ 200MHz
1.4
2.4
3.4
ns
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.136
ps
tsk(o)
Output Skew; NOTE 2, 5
145
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
1.3
ns
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
200
ƒ ≤ 100MHz
45
700
ps
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5F. AC Characteristics, V_DD = 2.5V ± 5%, V_DDO = 1.8V ± 0.2V, T_A = 0°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tjit
Output Frequency
200
MHz
Propagation Delay, Low to High; NOTE 1
ƒ ≤ 200MHz
1.5
2.6
3.7
ns
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.114
ps
tsk(o)
Output Skew; NOTE 2, 5
150
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
1.5
ns
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
200
ƒ ≤ 100MHz
45
700
ps
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
9
ICS8312AY REV. D JULY 3, 2008