ICS8312 Datasheet, PDF (7/18 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER

ICS8312
LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
AC Electrical Characteristics
Table 5A. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = 0°C to 85°C
Parameter Symbol
Test Conditions
f_MAX
tp_LH
tjit
Output Frequency
Propagation Delay, Low to High; NOTE 1
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
ƒ ≤ 250MHz
100MHz, Integration Range:
12kHz – 20MHz
tsk(o)
Output Skew; NOTE 2, 5
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
ƒ ≤ 200MHz
Minimum Typical Maximum Units
250
MHz
1.2
1.9
2.5
ns
0.037
ps
125
ps
800
ps
200
700
ps
45
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V_DD = V_DDO = 2.5V ± 5%, T_A = 0°C to 85°C
Parameter Symbol
Test Conditions
f_MAX
tp_LH
tjit
Output Frequency
Propagation Delay, Low to High; NOTE 1
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
ƒ ≤ 250MHz
100MHz, Integration Range:
12kHz – 20MHz
tsk(o)
Output Skew; NOTE 2, 5
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
ƒ ≤ 150MHz
Minimum Typical Maximum Units
250
MHz
1.4
2.3
3.2
ns
0.022
ps
150
ps
1.1
ns
200
700
ps
45
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
7
ICS8312AY REV. D JULY 3, 2008