ICS8312 Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER

ICS8312
LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 5, 8, 12, 16,
17, 21, 25, 29
2, 7
3
Name
GND
V_DD
CLK_EN
4
CLK
6
OE
9, 11, 13, 15,
18, 20, 22, 24,
26, 28, 30, 32
10, 14, 19, 23,
27, 31
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
V_DDO
Type
Description
Power
Power supply ground.
Power
Input
Input
Input
Pullup
Pulldown
Pullup
Positive supply pins.
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q[0:11].
LVCMOS / LVTTL interface levels.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
C_PD
Power Dissipation Capacitance
(per output)
R_OUT
Output Impedance
Test Conditions
V_DDO = 3.465V
V_DDO = 2.625V
V_DDO = 2V
V_DDO = 3.3V ± 5%
V_DDO = 2.5V ± 5%
V_DDO = 1.8V ± 0.2V
Minimum
Typical
4
51
51
7
7
10
Maximum
19
18
16
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
2
ICS8312AY REV. D JULY 3, 2008