9LPRS436C Datasheet, PDF (9/20 Pages) Integrated Device Technology – Low Power Clock for Intel Atom®-Based Systems

9LPRS436C
Low Power Clock for Intel Atom^®-Based Systems
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
C OND ITIONS
M IN
TYP
MAX UNITS Notes
Clk Stabilization
T_STAB
From VDD Power-Up or de-assertion of PD to
1st clock
1.1
1 .8
ms
Td ri ve _PE REQ _o ff
Td ri ve _PE REQ _o n
Tdrive_CPU
T_{D RPER OFF}
TD RPERON
T_{DRSR C}
Output stop after PEREQ# deasserted
Output run after PEREQ# asserted
CPU output enable after
CPU_STOP# de-assertion
2
3
clocks
2
3
clocks
8
10
ns
Tdrive_PCIEX
T_{D RPC IEX}
PCIEX output enable after
PCI&PCIEX_STOP# de-assertion
8
15
ns
1
Tfall_SE
Trise_SE
Td riv e_P D#
T_FALL
TR ISE
T_{D RPD}
Fall/rise time of all 3.3V control inputs from 20-
80%
Differential output enable after
PD# de-assertion
10
ns
10
ns
85
300
us
1
AC Electrical Characteristics - CPU, PCIEX, SATA, DOT96MHz
PARAMETER
SYMBOL
C OND ITIONS
Rising Edge Slew Rate
tSLR
Differential Measurement
Falling Edge Slew Rate
tFL R
Differential Measurement
Slew Rate Variation
tSLVAR
Single-ended Measurement
Maximum Output Voltage
VHIGH
Includes overshoot
Minimum Output Voltage
VL OW
Includes undershoot
Differential Voltage Swing
VSWING
Differential Measurement
Crossing Point Voltage
VXABS
Single-ended Measurement
Crossing Point Variation
VXABSVAR
Single-ended Measurement
Duty Cycle
DCYC
Differential Measurement
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
CPU2_IPT Jitter - Cycle to Cycle
CPU2JC2C
Differential Measurement
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
SATA Jitter - Cycle to C ycle
SATAJC2C
Differential Measurement
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
SRC Skew
SRCSKEW
Differential Measurement
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CON DITIONS
Output Impedance
RDSP
VO = VDD*(0.5)
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Tperiod
33.33MHz output no spread
33.33MHz output spread
Absolute min/max period
Tabs
33.33MHz output no spread
33.33MHz output nominal/spread
Output High Voltage
Output Low Voltage
Output High Current
V_OH
I_OH = -1 mA
VOL
IOL = 1 mA
IOH
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
Output Low Current
IOL
VOL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
Falling Edge Slew Rate
t_{F LR}
Measured from 2.0 to 0.8 V
Duty Cycle
d _t1
V_T = 1.5 V
Pin to Pin Skew
t skew
VT = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
*TA = Tambient; VDD = 3.3 V +/-5%; CL=5pF, Rs= 22Ω (unless specified otherwise)
V_T = 1.5 V
1 _{Guaranteed by design and characterization, not 100% tested in p rod uction.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
3 _{Slew rate emastured through V_swing voltage range cente red about differential zero}
4 _{Vcross is defined at the voltage where Clock = Clock#.}
5 _{Only appli es to the differential rising edge (Clock rising, Clock# falling.)}
6 _{CPU group skew is nominally 0ps.}
M IN
2.5
2.5
-30 0
30 0
30 0
45
TYP
3.3
3.2
16
80 6
39 5
32
49.7
66
12 5
66
66
65
38
14 5
44
MAX
4
4
20
1150
550
140
55
85
150
125
125
250
100
150
250
UNITS NOTES
V/ns 1,2
V/ns 1,2
%
1
mV
1
mV
1
mV
1
mV 1,3,4
mV 1,3,5
%
1
ps
1
ps
1
ps
1
ps
1
ps
1
ps
1, 6
ps
1, 6
ps
1
M IN
TYP
12
-10 0
29 .9970 0
30 .0842 1
29 .4970 0
29 .5661 7
2.4
-33
30
1
1.7
1
1.8
45
50.6
15 0
MAX
55
100
30.0 0300
30.2 3459
30.5 0300
30.5 8421
0 .4
-33
38
4
4
55
250
500
UNITS
Ω
ppm
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
%
ps
ps
NOTES
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
IDT^® Low Power Clock for Intel Atom^®-Based Systems
9
1561C — 08/24/11