9LPRS436C Datasheet, PDF (8/20 Pages) Integrated Device Technology – Low Power Clock for Intel Atom®-Based Systems

9LPRS436C
Low Power Clock for Intel Atom^®-Based Systems
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
C OND ITIONS
3.3V Core Supply Voltage
VDDA
3.3V Logic Supply Voltage
VDD
Input Low Voltage
VIL
Input High Voltage
V _IH
Except for SMBus interface
Input High Voltage
V _{IHS MB}
SMBus clock and data pins
Storage Temperature
Ts
Case Temperature
Tca se
Input ESD protection
ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied nor guaranteed.}
M IN
GND-0 .5
-6 5
20 00
TYP
MAX
4 .6
4 .6
V _DD +0.5 V
5.5V
150
115
UNITS
V
V
V
V
V
°_C
°C
V
NOTES
1, 2
1, 2
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
SYMBOL
C OND ITIONS
Ambient Operating Temp
T_{amb C}
Tam b_I
Standard Device
Industrial Temperature R ange Device
Supply Voltage
VDDxxx
Supply Voltage
Input High Voltage
Input Low Voltage
V_{I HSE}
VILSE
Single-ended 3.3V inputs
Single-ended 3.3V inputs
M IN
0
-40
3.135
2
VSS - 0.3
TYP
FS(4:3) Input High Voltage
V _{IH_F S 4}
Single-ended 3.3V FS(4:3) Inputs
2
FS(4:3) Input Low Voltage
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
V_{IL_ FS4}
V IH_F S
VIL _FS
Single-ended 3.3V FS(4:3) Inputs
3.3 V +/-5%
3.3 V +/-5%
V_SS - 0.3
0.7
VSS - 0.3
Input Leakage Current
Input Leakage Current
Output High Voltage
IIN
I_INRES
V O HSE
VIN = VDD , VIN = GND
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
Single-ended outputs, IOH = -1mA
-5
-20 0
2.4
Output Low Voltage
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOLSM B = 0 .4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/D ata Fall Time
VOLSE
I _{DDVD D3.3}
ID DVD DSUSP3 .3
I_{D DPD VDD3 .3}
ID DPD SUSP3.3w
I_{DD PDSU SP3.3}
F_i
L pin
C_IN
CO UT
C_{IN X}
V _DD
VO LSMB
I _{PULLU P}
TR I2C
TF I2C
Single-ended outputs, IOL = 1 mA
Full Active, C_L = Full load; IDD 3.3V
Full Active, CL = Full load; IDD 3.3V
3.3V Main Rail
VDD_SUSP Rail. 25MHz Running (WOL)
VDD_SUSP Rail. 25MHz Off
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
@ IPUL LUP
SMB Data Pin
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
10 6
12
12
3
1.5
2.7
4
Maximum SMBus Operating Frequency
Spread Spectrum Modulation Frequency
FSMBUS
f_{SSM OD}
Triangular Modulation
30
32.5
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 _{Operation at these points is not recommended}
2 _{Maximum VIH is not to exceed VDD}
3 _{Human Body Model}
4 _{Operation under these conditions is nei ther implied, nor guaranteed.}
5_{S ignal is required to be monotonic in this region.}
6 _{Input leakage current does not include inputs with pull-up or pull-down resistors}
7 _{3.3V referenced inputs are: PCI&P CIEX_STOP #, CPU_STOP #, ITP_EN, SCLK, SDATA, VTT_PWR_GD/P D#, SEL12_48# and PEREQ# inputs if selected.}
8 _{For margining purposes only. Normal operation should have Fin = 25MHz +/-50ppm}
MAX
85
85
3. 465
V_DD + 0 .3
0 .8
UNITS
°C
°C
V
V
V
VDD + 0.3 V
0 .8
V
VDD+0.3 V
0 .35
5
200
0 .4
115
15
0
15
4
27
7
5
6
6
5 .5
0 .4
V
uA
uA
V
V
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
V
V
mA
1000
ns
300
ns
100
kH z
33
kH z
No tes
7
7
6
5
5
8
IDT^® Low Power Clock for Intel Atom^®-Based Systems
8
1561C — 08/24/11