89HPES8T5 Datasheet, PDF (9/31 Pages) Integrated Device Technology – Low-latency cut-through switch architecture

IDT 89HPES8T5 Data Sheet
Pin Characteristics
Note: Some input pads of the PES8T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
Pin Name Type Buffer
I/O
Type
Internal
Resistor¹
PCI Express Inter- PE0RN[3:0]
I
face
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE2RN[0]
I
PE2RP[0]
I
PE2TN[0]
O
PE2TP[0]
O
PE3RN[0]
I
PE3RP[0]
I
PE3TN[0]
O
PE3TP[0]
O
PE4RN[0]
I
PE4RP[0]
I
PE4TN[0]
O
PE4TP[0]
O
PE5RN[0]
I
PE5RP[0]
I
PE5TN[0]
O
PE5TP[0]
O
PEREFCLKN[2:1]
I
PEREFCLKP[2:1]
I
REFCLKM
I
SMBus
MSMBADDR[4:1]
I
MSMBCLK
I/O
MSMBDAT
I/O
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
SSMBDAT
I/O
General Purpose I/O GPIO[10:0]
I/O
CML Serial Link
LVPECL/
CML
LVTTL
LVTTL
LVTTL
Diff. Clock
Input
Input
Input
STI²
STI
Input
STI
STI
High Drive
pull-down
pull-up
pull-up
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
Notes
Refer toTable 9
pull-up on board
pull-up on board
pull-up on board
pull-up on board
9 of 31
March 27, 2008