89HPES8T5 Datasheet, PDF (2/31 Pages) Integrated Device Technology – Low-latency cut-through switch architecture

IDT 89HPES8T5 Data Sheet
◆ _{Testability and Debug Features}
– Ability to read and write any internal register via the SMBus
◆ _{Eleven General Purpose Input/Output pins}
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆ _{Packaged in 19mm x 19mm 324-ball BGA with 1mm ball spacing}
Product Description
Utilizing standard PCI Express interconnect, the PES8T5 provides the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum number of board layers. It provides connectivity for up to 5 ports across 8 integrated
serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1.
The PES8T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
tion layers. The PES8T5 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transac-
tions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for
applications requiring additional narrow port connectivity.
Processor
Processor
North
Bridge
MMMeMemememomororyoryryy
South
Bridge
x4
PES8T5
x1
x1 x1
GE
LOM
GE
LOM
GE
x1
1394
Figure 2 I/O Expansion Application
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March 27, 2008