89HPES8T5 Datasheet, PDF (13/31 Pages) Integrated Device Technology – Low-latency cut-through switch architecture

IDT 89HPES8T5 Data Sheet
1. _{Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1}
Signal
Symbol
Reference
Edge
Min
Max Unit
Timing
Diagram
Reference
GPIO
GPIO[10:0]¹
Tpw_13b²
None
50 — ns See Figure 6.
Table 11 GPIO AC Timing Characteristics
1. _{GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if}
they are asynchronous.
2. _{The values for this symbol were determined by calculation, not by testing.}
EXTCLK
GPIO (synchronous output)
GPIO (asynchronous input)
Tdo_13a
Tpw_13b
Tdo_13a
Figure 6 GPIO AC Timing Waveform
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK
JTAG_TMS¹,
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
Tper_16a
none
50.0
—
Thigh_16a,
Tlow_16a
10.0
25.0
Tsu_16b
JTAG_TCK rising
2.4
—
Thld_16b
1.0
—
Tdo_16c
JTAG_TCK falling
—
20
Tdz_16c²
—
20
Tpw_16d²
none
25.0
—
ns
See Figure 7.
ns
ns
ns
ns
ns
ns
Table 12 JTAG AC Timing Characteristics
1. _{The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N}
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2. _{The values for this symbol were determined by calculation, not by testing.}
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March 27, 2008