831752_16 Datasheet, PDF (9/18 Pages) Integrated Device Technology – Clock Switch for ATCA/AMC and PCIe Applications

831752 Data Sheet
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
FCLK/nFCLK Pins
In case FCLK/nFCLK are unused, one of the following two
configurations can be used: either FCLK/nFCLK are configured as
an output (DIR_SEL = 1) and left floating, or FCLK/nFCLK are
configured as an input (DIR_SEL = 0). In this case 1k pulldown is
required on FCLK and 1k Pullup is required on nFCLK.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V₁= V_DD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V₁in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and V_DD = 3.3V,
R1 and R2 value should be adjusted to set V₁ at 1.25V. The values
below are for when both the single ended swing and V_DD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be
100. The values of the resistors can be increased to reduce the
loading for slower and weaker LVCMOS driver. When using
single-ended signaling, the noise rejection benefits of differential
signaling are reduced. Even though the differential input can handle
full rail LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V_IL cannot be less
than -0.3V and V_IH cannot be more than V_DD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
©2016 Integrated Device Technology, Inc
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Revision B June 28, 2016