831752_16 Datasheet, PDF (10/18 Pages) Integrated Device Technology – Clock Switch for ATCA/AMC and PCIe Applications

831752 Data Sheet
3.3V Differential Clock Input Interface
The CLK/nCLK accepts HCSL, LVDS and LVPECL and other
differential signals. Both differential signals must meet the V_PP and
V_CMR input requirements. Figures 2A to 2E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements. The figures below also apply to FCLK/
nFCLK operating as an input.
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
Figure 3A. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver
Figure 3B. CLK/nCLK Input Driven by a 3.3V HCSL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
Differential
R1
R2
84
84
Input
Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver with AC Couple
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Differential
Input
Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver
©2016 Integrated Device Technology, Inc
10
Revision B June 28, 2016