IDT82P2828_09 Datasheet, PDF (83/154 Pages) Integrated Device Technology – 28(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2828
CLKG - CLKT1 & CLKE1 Generation Control Register
Address: 1C0H
Type: Read / Write
Default Value: 0FH
7
6
5
-
-
-
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
4
3
2
1
0
-
CLKE1_EN
CLKE1
CLKT1_EN
CLKT1
Bit
Name
Description
7-4
-
Reserved.
3
CLKE1_EN This bit controls whether the output on the CLKE1 pin is enabled.
0: The output is disabled. CLKE1 is in High-Z state.
1: The output is enabled. The frequency of CLKE1 is determined by the CLKE1 bit (b2, CLKG). (default)
2
CLKE1 This bit is valid only when the CLKE1_EN bit (b3, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKE1 pin.
0: 8 KHz.
1: 2.048 MHz. (default)
1
CLKT1_EN This bit controls whether the output on the CLKT1 pin is enabled.
0: The output is disabled. CLKT1 is in High-Z state.
1: The output is enabled. The frequency of CLKT1 is determined by the CLKT1 bit (b0, CLKG). (default)
0
CLKT1 This bit is valid only when the CLKT1_EN bit (b1, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKT1 pin.
0: 8 KHz.
1: 1.544 MHz. (default)
REFCF - REFA/B Output Configuration Register
Address: 200H
Type: Read / Write
Default Value: 30H
7
6
5
-
JA_BYPAS
REFH
4
FS_BYPAS
3
FREE
2
FREQ2
1
FREQ1
0
FREQ0
Bit
Name
Description
7
-
Reserved.
6
JA_BYPAS This bit is valid only when the clock source for REFA or REFB is the recovered clock of one of the 29 channels in the correspond-
ing receiver. This bit determines whether the selected recovered clock passes through the RJA.
0: The selected recovered clock is derived from the output of RJA. (default)
1: The selected recovered clock does not pass through the RJA and is derived from the output of Rx Clock & Data Recovery.
5
REFH This bit is valid only when the selected clock source is lost. This bit controls the output on REFA/REFB.
For REFA, this bit, together with the FS_BYPAS bit (b4, REFCF) and the FREE bit (b3, REFCF), controls the output on REFA
when the selected clock source is the recovered clock of one of the 29 channels; this bit is ignored when the selected clock
source is CLKA. Refer to the related table in the description of the FREE bit (b3, REFCF).
For REFB:
0: Output free running clock. The frequency is 1.544 MHz if the selected clock source was T1 clock or 2.048 MHz if the selected
clock source was E1 clock.
1: Output high level. (default)
4
FS_BYPAS This bit determines whether the selected clock source for REFA passes through an internal Frequency Synthesizer.
0: The internal Frequency Synthesizer is enabled.
1: The internal Frequency Synthesizer is bypassed. (default)
Programming Information
83
February 6, 2009