IDT82P2828_09 Datasheet, PDF (26/154 Pages) Integrated Device Technology – 28(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2828
Name
SDO / ACK / RDY
I/O
Output
D[0]
Output / Input
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
A[0]
Input
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
TRST
Input
Pull-Down
TMS
Input
Pull-up
TCK
Input
Pin No.
AJ16
AG12
AH12
AJ12
AK12
AG11
AH11
AJ11
AK11
AH15
AJ15
AK15
AG14
AH14
AJ14
AK14
AG13
AH13
AJ13
AK13
AF4
AE5
AF6
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Description
SDO: Serial Data Output
In Serial microprocessor interface, this multiplex pin is used as SDO.
Data on this pin is serially clocked out of the device on the falling edge of SCLK.
ACK: Acknowledge Output (Active Low)
In Parallel Motorola microprocessor interface, this multiplex pin is used as ACK.
A low level on ACK indicates that valid information on the data bus is ready for a read opera-
tion or acknowledges the acceptance of the written data during a write operation.
RDY: Ready Output
In Parallel Intel microprocessor interface, this multiplex pin is used as RDY.
A high level on RDY reports to the microprocessor that a read/write cycle can be completed. A
low level on RDY reports that wait states must be inserted.
D[7:0]: Bi-directional Data Bus
In Parallel Motorola /Intel Non-Multiplexed microprocessor interface, these pins are the bi-
directional data bus of the microprocessor interface.
In Parallel Motorola /Intel Multiplexed microprocessor interface, these pins are the multiplexed
bi-directional address /data bus.
In Serial microprocessor interface, these pins should be connected to GNDD.
A[10:0]: Address Bus
In Parallel Motorola /Intel Non-Multiplexed microprocessor interface, these pins are the
address bus of the microprocessor interface.
In Parallel Motorola /Intel Multiplexed microprocessor interface, A[10:8], together with D[7:0],
are the address bus; while A[7:0] should be connected to GNDD.
In Serial microprocessor interface, these pins should be connected to GNDD.
JTAG (per IEEE 1149.1)
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
Pin Description
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February 6, 2009