IDT82P2828_09 Datasheet, PDF (22/154 Pages) Integrated Device Technology – 28(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2828
Name
I/O
MCLK
Input
MCKSEL[0]
Input
MCKSEL[1]
MCKSEL[2]
MCKSEL[3]
CLKT1
Output
CLKE1
Output
Pin Description
Pin No.
AK19
AF19
AF20
AF21
AF22
AH18
AG18
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Description
Clock
MCLK: Master Clock Input
MCLK provides a stable reference timing for the IDT82P2828. MCLK should be a clock with +/
-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK
is informed to the device by MCKSEL[3:0].
If MCLK misses (duty cycle is less than 30% for 10 µs) and then recovers, the device will be
reset automatically.
MCKSEL[3:0]: Master Clock Selection
These four pins inform the device of the clock frequency input on MCLK:
MCKSEL[3:0]^*
Frequency (MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Note:
0: GNDD
1: VDDIO
1.544
1.544 X 2
1.544 X 3
1.544 X 4
1.544 X 5
1.544 X 6
1.544 X 7
1.544 X 8
2.048
2.048 X 2
2.048 X 3
2.048 X 4
2.048 X 5
2.048 X 6
2.048 X 7
2.048 X 8
CLKT1: 8 KHz / T1 Clock Output
The output on CLKT1 can be enabled or disabled, as determined by the CLKT1_EN bit (b1,
CLKG).
When the output is enabled, CLKT1 outputs an 8 KHz or 1.544 MHz clock, as selected by the
CLKT1 bit (b0, CLKG). The output is locked to MCLK.
When the output is disabled, CLKT1 is in High-Z state.
CLKE1: 8 KHz / E1 Clock Output
The output on CLKE1 can be enabled or disabled, as determined by the CLKE1_EN bit (b3,
CLKG).
When the output is enabled, CLKE1 outputs an 8 KHz or 2.048 MHz clock, as selected by the
CLKE1 bit (b2, CLKG). The output is locked to MCLK.
When the output is disabled, CLKE1 is in High-Z state.
22
February 6, 2009