IDT82V2048S Datasheet, PDF (8/62 Pages) Integrated Device Technology – OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT WITH SINGLE ENDED OPTION

IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Pin No.
Type
TQFP144 PBGA160
Description
TS2: Template Select 2
In hardware control mode, the signal on this pin is the most significant bit for the transmit template select.
Refer to 2.5.1 Waveform Shaper for details.
TS2/SCLK/
ALE/AS
I
SCLK: Shift Clock
In serial host mode, the signal on this pin is the shift clock for the serial interface. Data on pin SDO is
clocked out on falling edges of SCLK if pin CLKE is high, or on rising edges of SCLK if pin CLKE is low.
Data on pin SDI is always sampled on rising edges of SCLK.
86
J12
ALE: Address Latch Enable
In parallel Intel multiplexed host mode, the address on AD[4:0] is sampled into the device on the falling
edges of ALE (signals on AD[7:5] are ignored). In non-multiplexed host mode, ALE should be pulled high.
TS1/RD/R/W
I
AS: Address Strobe (Active Low)
In parallel Motorola multiplexed host mode, the address on AD[4:0] is latched into the device on the falling
edges of AS (signals on AD[7:5] are ignored). In non-multiplexed host mode, AS should be pulled high.
TS1: Template Select 1
In hardware control mode, the signal on this pin is the second most significant bit for the transmit template
select. Refer to 2.5.1 Waveform Shaper for details.
85
J13
RD: Read Strobe (Active Low)
In parallel Intel multiplexed or non-multiplexed host mode, this pin is active low for read operation.
R/W: Read/Write Select
In parallel Motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and
high for read operation.
TS0: Template Select 0
In hardware control mode, the signal on this pin is the least significant bit for the transmit template select.
Refer to 2.5.1 Waveform Shaper for details.
TS0/SDI/WR/
DS
I
SDI: Serial Data Input
In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on the rising
edges of SCLK.
WR: Write Strobe (Active Low)
84
J14 In parallel Intel host mode, this pin is active low during write operation. The data on D[7:0] (in non-multi-
plexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges of WR.
DS: Data Strobe (Active Low)
In parallel Motorola host mode, this pin is active low. During a write operation (R/W = 0), the data on D[7:0]
(in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges
of DS. During a read operation (R/W = 1), the data is driven to D[7:0] (in non-multiplexed mode) or AD[7:0]
(in multiplexed mode) by the device on the rising edges of DS.
In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus
A[4:0] are latched into the device on the falling edges of DS.
8