IDT82V2048S Datasheet, PDF (51/62 Pages) Integrated Device Technology – OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT WITH SINGLE ENDED OPTION

IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
TRANSCEIVER TIMING CHARACTERISTICS
INDUSTRIAL TEMPERATURE RANGES
Symbol
Parameter
Min
Typ
Max
Unit
MCLK Frequency
E1:
2.048
MHz
T1:
1.544
MHz
MCLK Tolerance
-100
100
ppm
MCLK Duty Cycle
40
60
%
Transmit Path
TCLK Frequency
E1:
2.048
MHz
T1:
1.544
MHz
TCLK Tolerance
-50
+50
ppm
TCLK Duty Cycle
10
90
%
t1
Transmit Data Setup Time
40
ns
t2
Transmit Data Hold Time
40
ns
Delay time of OE low to driver High-Z
1
µs
Delay time of TCLK low to driver High-Z
40
44
48
µs
Receive Path
Clock Recovery Capture Range⁽¹⁾
E1:
± 80
ppm
T1:
RCLK Duty Cycle⁽²⁾
± 180
ppm
40
50
60
%
t4
RCLK Pulse Width⁽²⁾
E1:
457
488
519
ns
T1:
607
648
689
ns
t5
RCLK Pulse Width Low Time
E1:
203
244
285
ns
T1:
259
324
389
ns
t6
RCLK Pulse Width High Time
E1:
203
244
285
ns
T1:
259
324
389
ns
Rise/Fall Time⁽³⁾
5
30
ns
t7
Receive Data Setup Time
E1:
200
244
ns
T1:
200
324
ns
t8
Receive Data Hold Time
E1:
200
244
ns
T1:
200
324
ns
t9
RDPn/RDNn Pulse Width (MCLK = High)⁽⁴⁾
E1:
200
244
ns
T1:
300
324
ns
1. _{Relative to nominal frequency, MCLK = ± 100 ppm}
2. _{RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 UI dis-}
placement for E1 per ITU G.823).
3. _{For all digital outputs. C load = 15 pF}
4. _{Clock recovery is disabled in this mode.}
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