IDT77V107 Datasheet, PDF (8/24 Pages) Integrated Device Technology – Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2

IDT77V107
To declare 'Bad Signal' (from "Good" to "Bad"):
The same up-down counter counts from 0 to 7 (being at 0 to provide
a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the counter increases by one. If it detects all "good symbols" and no
"bad symbols" in the next time period, the counter decreases by one.
The "Bad Signal" is declared when the counter reaches 7. The Good
Signal Bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at
least one "bad symbol" is detected in each of seven consecutive groups
of 204.8 symbols.
8kHz Timing Marker
The 8kHz timing marker, described earlier, is a completely optional
feature which is essential for some applications requiring synchroniza-
tion for voice or video, and unnecessary for other applications. When
unused, TXREF should be tied high. Also note that it is not limited to
8kHz, should a different frequency be desired. When looped, a received
X_8 command byte causes one to be generated on the transmit side.
A received X_8 command byte causes the 77V107 to issue a nega-
tive pulse on RXREF. The source channel of the marker is program-
mable.
Utopia Level 2 PHY-ATM Interface
UTOPIA Level 2 is a Physical Layer to ATM Layer interface standard-
ized by the ATM Forum. It is selected using the M1 and M0 pins. It trans-
fers ATM cells and has separate transmit and receive channels and
specific handshaking protocols. UTOPIA Level 2 has dedicated address
signals for both the transmit and receive directions that allow the ATM
layer device to specify which PHY device it is communicating with. It is
defined in ATM Forum document af-phy-0039.
Note that the 77V107 supports the standard "Operation with 1
TxClav and 1 Rx Clav" multi-phy scheme from the Utopia Level 2 stan-
dard. The optional Multiplexed Status Polling multi-phy scheme is not
directly supported.
There is a single 8-bit data bus in the transmit (ATM-to-PHY) direc-
tion, and a single 8-bit data bus in the receive (PHY-to-ATM) direction. In
addition to the data bus, each direction also includes a single optional
parity bit, an address bus, and several handshaking signals. The
UTOPIA address of the PHY is determined by bits 4 to 0 in the
Enhanced Control Register. Please note that the transmit bus and the
receive bus operate completely independently. The Utopia signals are
summarized below:
TXDATA[7:0]
TXPARITY
TXSOC
TXADDR[4:0]
TXEN
TXCLAV
TXCLK
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
RXDATA[7:0]
RXPARITY
RXSOC
RXADDR[4:0]
RXEN
RXCLAV
RXCLK
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
The ATM device starts by polling the PHY ports on the Utopia bus to
determine if any of them has room to accept a cell for transmission
(TXCLAV), or has a receive cell available to pass on to the ATM device
(RXCLAV). To poll, the ATM device drives an address (TXADDR or
RXADDR) then observes TXCLAV or RXCLAV on the next cycle of
TXCLK or RXCLK. The PHY will tri-state TXCLAV and RXCLAV except
when it is addressed.
If TXCLAV or RXCLAV is asserted, the ATM device may select the
PHY, then transfer a cell to or from it. Selection of a PHYis performed by
driving the address of the desired port while TXEN or RXEN is high,
then driving TXEN or RXEN low. When TXEN is driven low, TXSOC
(start of cell) is driven high to indicate that the first byte of the cell
isbeing driven on TXDATA. The ATM device may chose to temporarily
suspend transfer of the cell by deasserting TXEN. Otherwise, TXEN
remains asserted as the next byte is driven onto TXDATA with each
cycle of TXCLK.
In the receive direction, the ATM device selects a PHY if it wishes to
receive the cell that the PHY is holding. It does this by asserting RXEN.
The PHY then transfers the data 8 bits each clock cycle, as determined
by RXEN. As in the transmit direction, the ATM device may suspend
transfer by deasserting RXEN at any time. Note that the PHY asserts
RXSOC coincident with the first byte of each cell.
TXPARITY and RXPARITY are parity bits for the corresponding 8-bit
data fields. Odd parity is used, which means that for an all-zero data
pattern, the corresponding parity bit is one.
The following figures may be referenced for Utopia Level 2 bus
examples.
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July 3, 2001