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IDT77V107 Datasheet, PDF (1/24 Pages) Integrated Device Technology – Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
Single ATM PHY for 25.6 and
51.2 Mbps with Utopia Level 2
IDT77V107
Features List
! Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions of the
Physical Layer
! Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
! Also operates at 51.2Mbps
! 8-bit Utopia Level 2 Interface
! 3-Cell Transmit & Receive FIFOs
! Receiver Auto-Synchronization and Good Signal Indication
! Supports UTP Category 3 physical media
! Interfaces to standard magnetics
! Low-Power CMOS
! 3.3V supply with 5V tolerant inputs
! 100-lead TQFP Package (14 x 14 mm)
! Commercial and Industrial temperature ranges
Description
The IDT77V107 is a member of IDT's family of products supporting
Asynchronous Transfer Mode (ATM) data communications and
networking. The IDT77V107 implements the physical layer for 25.6
Mbps ATM, connecting a serial copper link (UTP Category 3) to an ATM
layer device such as a SAR or a switch ASIC. The IDT77V107 also
operates at 51.2 Mbps and is well suited to backplane driving applica-
tions. The 77V107 has an 8-bit UTOPIA Level 2 interface on the cell
side.
The IDT77V107 is fabricated using IDT's state-of-the-art CMOS tech-
nology, providing the highest levels of integration, performance and reli-
ability, with the low-power consumption characteristics of CMOS.
77V107 Overview
The 77V107 is a physical layer interface chip for 25.6Mbps ATM
network communications as defined by ATM Forum document af-phy-
040.000 and ITU-T I.432.5. The physical layer is divided into a Physical
Media Dependent sub layer (PMD) and Transmission Convergence (TC)
sub layer. It is based on the 77V106.
The PMD sub layer includes the functions for the transmitter, receiver
and clock recovery for operation across 100 meters of category 3
unshielded twisted pair (UTP) cable. This is referred to as the Line Side
Interface.
The TC sub layer defines the line coding, scrambling, data framing
and synchronization. Transmitted cells are first scrambled, then pass
through a 4b5b encoder and are finally NRZI encoded. In the 4b5b
encoder, 4-bit nibbles are converted to 5-bit symbols via a look-up table.
In addition to the 16 valid data symbols, a 17th symbol is used for a
special escape (X) symbol. This symbol has the property of being
Functional Block Diagram
TxREF
TxAddr[4:0]
TxCLK
TxDATA 9
TxSOC
TxEN
TXCLAV
ALE
WR
RD
CS
AD[7:0] 8
INT
RESET
3 CELL FIFO
UTILITY
BUS
CONTROLLER
RxAddr[4:0]
RxCLK
RxDATA 9
RxSOC
RxEN
RXCLAV
RxREF
M1, M0
3 CELL FIFO
MODE SELECT
 2001 Integrated Device Technology, Inc.
TxLED
SCRAMBLER
PRNG
4B/5B
ENCODER
P/S
NRZI
Line
Driver
TXD+
TXD-
RESET
LOOP BACK
DESCRAMBLER
5B/4B
DECODER
S/P
DNRZI
RxLED
1 of 24
77V107
CLK
REC
Line
RxVR
RxD+
RxD-
OSC
5362 drw 01
July 3, 2001
DSC 5362/2