IDT77V107 Datasheet, PDF (12/24 Pages) Integrated Device Technology – Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2

IDT77V107
Control and Status Interface
Utility Bus
The Utility Bus is a byte-wide interface that provides access to the
registers within the IDT77V107. These registers are used to select
desired operating characteristics and functions, and to communicate
status to external systems.
The Utility Bus is implemented using a multiplexed address and data
bus (AD[7:0]) where the register address is latched via the Address
Latch Enable (ALE) signal.
The Utility Bus interface is comprised of the following pins:
AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms. A register read is
performed as follows:
1. Initial condition:
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
2. Set up register address:
– place desired register address on AD[7:0]
– set ALE to logic 1;
– latch this address by setting ALE to logic 0.
3. Read register data:
– Remove register address data from AD[7:0]
– assert CS by setting to logic 0;
– assert RD by setting to logic 0
– wait minimum pulse width time (see AC specifications)
Write Operation
A register write is performed as described below:
1. Initial condition:
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
2. Set up register address:
– place desired register address on AD[7:0]
– set ALE to logic 1;
– latch this address by setting ALE to logic 0.
3. Write data:
– place data on AD[7:0]
– assert CS by setting to logic 0;
– assert WR (logic 0) for minimum time (according to timing
specification); reset WR or CS to logic 1 to complete register
write cycle.
Interrupt Operations
A variety of selectable interrupt and signalling conditions are
provided. They are useful both during ‘normal’ operation, and as diag-
nostic aids. Refer to the Status and Control Register List section.
Overall interrupt control is provided via bit 0 of the Master Control
Register. When this bit is cleared (set to 0), interrupt signalling is
prevented on the respective port. The Interrupt Mask Register allows
individual masking of different interrupt sources. Additional interrupt
signal control is provided by bit 5 of the Master Control Register. When
this bit is set (=1), receive cell errors will be flagged via interrupt signal-
ling and all other interrupt conditions are masked. These errors include:
– Bad receive HEC
– Short (fewer than 53 bytes) cells
– Received cell symbol error
Normal interrupt operations are performed by setting bit 0 and
clearing bit 5 in the Master Control Register. INT (pin 34) will go to a low
state when an interrupt condition is detected. The external system
should then interrogate the 77V107 to determine which one (or more)
conditions caused this flag, and reset the interrupt for further occur-
rences. This is accomplished by reading the Interrupt Status Register.
Decoding the bits in this byte will tell which error condition caused the
interrupt. Reading these registers also:
– clears the (sticky) interrupt status bits in the registers that are
read
– resets INT
This leaves the interrupt system ready to signal an alarm for further
problems.
LED Control and Signalling
The LED outputs provide bi-directional LED drive capability of 8 mA.
As an example, the RxLED outputs are described in the truth table:
State
Pin Voltage
Cells being transmitted
Low
Cells not being received
High
As illustrated in the following figure, this could be connected to
provide for a two-LED condition indicator. These could also be different
colors to provide simple status indication at a glance. (The minimum
value for R should be 330Ω).
TxLED Truth Table
State
Cells being transmitted
Cells not being received
Pin Voltage
Low
High
RxLED
TxLED
3.3V
R
(Indicates: Cells
being received or
transmitted)
(Indicates: Cells are
not being received or
R
transmitted)
Figure 11
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July 3, 2001