ICS9LPRS502 Datasheet, PDF (8/29 Pages) Integrated Device Technology – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
15 VDD48
16 USB_48MHz/FSLA
17 GND48
18 VDD96_IO
19 DOTT_96/SRCT0
20 DOTC_96/SRCC0
21 GND
22 VDD
23 SRCT1/SE1
24 SRCC1/SE2
25 GND
26 VDDPLL3_IO
27 SRCT2/SATAT
28 SRCC2/SATAC
TYPE
PWR
I/O
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
Power supply for USB clock, nominal 3.3V.
DESCRIPTION
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
Power supply for DOT96 output. 1.05 to 3.3V +/-5%.
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be
changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function
may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin for the DOT96 clocks.
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5%
downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz
SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
Power supply for PLL3 output. 1.05 to 3.3V +/-5%.
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
8
1125E—02/26/09