ICS9LPRS502 Datasheet, PDF (3/29 Pages) Integrated Device Technology – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description (continued)
PIN #
PIN NAME
17 SRCT1/SE1
18 SRCC1/SE2
TYPE
OUT
OUT
DESCRIPTION
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100
MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default
is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
19 GND
20 VDDPLL3_IO
21 SRCT2/SATAT
22 SRCC2/SATAC
23 GNDSRC
24 SRCT3/CR#_C
25 SRCC3/CR#_D
26 VDDSRC_IO
27 SRCT4
28 SRCC4
PWR
PWR
OUT
OUT
PWR
I/O
I/O
PWR
I/O
I/O
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
Power supply for PLL3 output. 1.05 to 3.3V +/-5%.
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin,
the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3
output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or
SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin,
the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3
output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
Power supply for SRC clocks. 1.05 to 3.3V +/-5%.
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
3
1125E—02/26/09