ICS9LPRS502 Datasheet, PDF (10/29 Pages) Integrated Device Technology – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
43 VDDSRC_IO
44 CPUC2_ITP/SRCC8
45 CPUT2_ITP/SRCT8
46 NC
47 VDDCPU_IO
48 CPUC1_F
49 CPUT1_F
50 GNDCPU
51 CPUC0
52 CPUT0
53 VDDCPU
54 CK_PWRGD/PD#
55 FSLB/TEST_MODE
56 GNDREF
TYPE
PWR
OUT
OUT
NC
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
DESCRIPTION
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
Not Connected
Power supply for CPU outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer
to Test Clarification Table.
Ground pin for crystal oscillator circuit
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
10
1125E—02/26/09