ICS9150-04 Datasheet, PDF (8/19 Pages) Integrated Circuit Systems – Pentium Pro™ and SDRAM Frequency Generator

ICS9150- 04
Byte 5: Peripheral Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
2
54
55
-
-
-
3
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reserved
IOAPIC2 (Act/Inact)
IOAPIC1 (Act/Inact)
Desktop Mode Only
IOAPIC0 (Act/Inact)
Reserved
Reserved
Reserved
REF0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 6: Peripheral Clock Register
BIT PIN# PWD
DESCRIPTION
Bit 7 - 1 Reserved
Bit 6 - 1 Reserved
Bit 5 - 1 Reserved
Bit 4 - 1 Reserved
Bit 3 - 1 Reserved
Bit 2 - 1 Reserved
Bit 1 - 1 Reserved
Bit 0 - 1 Reserve
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
ICS9150-04 Power Management Requirements
SIGNAL
CPU_ STOP#
PCI_STOP#
SIGNAL STATE
0 (Disabled)²
1 (Enabled)¹
0 (Disabled)²
1 (Enabled)¹
Latency
No. of rising edges of free
running PCICLK
1
1
1
1
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
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