ICS9150-04 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – Pentium Pro™ and SDRAM Frequency Generator

Definitions
5 Latched Inputs at Internal Power-On Reset:
Pin shared as
MODE ................................ 48MHz/MODE
CPU 3.3_2.5#V .................. IOAPIC2/CPU3.3#_2.5
FS0 ..................................... 24MHz/FS0
FS1 ..................................... PCICLK_F/FS1
FS2 ..................................... PCICLK0/FS2
2 Realtime Inputs
Pins 27, 28 - I²C Serial input SDATA & SCLK
ICS9150- 04
Pull-ups
2 pins with input latch or I/O have IOAPIC output function with VDDL1 which can be at 2.5V or 3.3V. These inputs will
have to use series resistor (above 100Ω) to external VIN to be 3.3 & 5V logic input tolerant.
PMOS output stage provides input clamp diode to VDDL.
• Nwell resistor Pull-ups 100 to 150KΩ to local VDD
(ie on IOAPIC pins use VDDL1, on FS1, 2 use VDD2, FS0=VDD4 and PCI_STOP#)
Functionality
V_DD1,2,3 = 3.3V±5%, V_DDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS2
FS1
FS0
CPU,
SDRAM(MHz)
PCICLK (MHz)
REF, IOAPIC
(MHz)
1
1
1
66.8
33.4 (1/2 CPU)
14.318
1
1
0
60.0
30.0 (1/2 CPU)
14.318
1
0
1
75.0
37.5 (1/2 CPU)
14.318
1
0
0
83.3
33.3
14.318
0
1
1
68.5
34.25 (1/2 CPU)
14.318
0
1
0
83.3
41.65 (1/2 CPU)
14.318
0
0
1
75.0
32
14.318
0
0
0
50.0
25.0 (1/2 CPU)
14.318
3