ICS8752I Datasheet, PDF (8/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS8752I
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7B. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
÷2
110
240
÷4
55
120
f_OUT
Output Frequency (PLL Mode)
÷6
36.67
80
÷8
27.5
60
÷12
18.33
40
f_VCO
PLL VCO Lock Range
t(Ø)
Static Phase Offset; NOTE 1
fVCO = 400MHz
Feedback ÷ 8
220
480
-90
50
190
tsk(b) Bank Skew; NOTE 2, 4
Measured on rising edge
at V_DDO/2
55
tsk(o) Output Skew; NOTE 3, 4
Measured on rising edge
at V_DDO/2
90
tjit(cc)
Cycle-to-Cycle
Jitter; NOTE 4
Different Frequencies
on Different Banks
All Outputs at
Same Frequency
400
75
t_L
PLL Lock Time
1
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
400
950
45
50
55
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
mS
ps
%
8752CYI
www.idt.com
8
REV. C JULY 30, 2010