ICS8752I Datasheet, PDF (6/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS8752I
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V_IH
Input High Voltage
V_DD = 3.3V
2
V = 2.5V
1.7
DD
V_IL
Input Low Voltage
V_DD = 3.3V
-0.3
V_DD = 2.5V
-0.3
DIV_ SELx0,
DIV_SELx1, CLK0,
V_DD = V_IN = 3.465V
I_IH
Input
CLK1, FB_IN, CLK_SEL,
High Current ^MR/nOE
or 2.625V
PLL_SEL
V_DD = V_IN = 3.465V
or 2.625V
DIV_ SELx0,
I_IL
Input
DIV_SELx1, CLK0,
CLK1, FB_IN, CLK_SEL,
V_DD = 3.465V or 2.625V,
V_IN = 0V
-5
Low Current ^MR/nOE
PLL_SEL
V_DD = 3.465V or 2.625V,
V_IN = 0V
-150
V_OH
Output High Voltage; NOTE 1
V_DDO = V_IN = 3.465V
2.6
V = V = 2.625V
1.8
DDO
IN
V_OL
Output Low Voltage; NOTE 1
NOTE
1:
Outputs
terminated
with
50Ω
to
V /2.
DDO
See
Parameter
Measurement
Information
section,
"Output Load Test Circuit" diagrams.
V_DD + 0.3
V + 0.3
DD
0.8
0.7
150
5
0.5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
f_REF
Parameter
Input Reference Frequency
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
Test Conditions
Minimum Typical Maximum Units
20
240
MHz
TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, V_DD = V_DDA = V_DDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
f_REF
Parameter
Input Reference Frequency
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
Test Conditions
Minimum Typical
20
Maximum
120
Units
MHz
8752CYI
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REV. C JULY 30, 2010