ICS87002-05 Datasheet, PDF (8/12 Pages) Integrated Device Technology – Third generation FemtoClock

ICS87002-05 Data Sheet
1:2 LVCMOS/LVTTL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER FOR AUDIO
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS87002-05.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87002-05 is the sum of the core power plus the power dissipation in the load(s). The following is the
power dissipation for V_DD = 3.3V + 0.3V = 3.6V, which gives worst case results.
Power (core)_MAX = V_{DD_MAX} * I_DD = 3.6V *85mA = 306mW
Total Static Power:
= Power (core)_MAX = 306mW
Dynamic Power Dissipation at F_{OUT_MAX} (24.576MHz)
Total Power (F_{OUT_MAX}) = [(C_PD * N) * Frequency * (V_DDO)²] = [(8pF *2) * 24.576MHz * (3.6V)²] = 5.1mW per output
N = number of outputs
Total Power
= Static Power + Dynamic Power Dissipation
= 306mW + 5.1mW
= 311mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that
the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 96°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.311W *96°C/W = 99.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 5. Thermal Resistance θ_JA for 8 Lead SOIC, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
96.0°C/W
1
87°C/W
2.5
82.0°C/W
ICS87002BM-05 REVISION B APRIL 16, 2010
8
©2010 Integrated Device Technology, Inc.