ICS87002-05 Datasheet, PDF (7/12 Pages) Integrated Device Technology – Third generation FemtoClock

ICS87002-05 Data Sheet
1:2 LVCMOS/LVTTL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER FOR AUDIO
Schematic Example
Figure 1 shows an example of ICS87002-05 application schematic.
In this example, the device is operated at V_DD = 3.3V. The input is
driven by a 3.3V LVCMOS driver. One example of an LVCMOS
termination is shown in this schematic. The decoupling capacitors
should be located as close as possible to the power pin.
Q1
R1
33
Driv er_LVCMOS
Zo = 50
VDD
C1
0.1u
U1
1
2
3
4
REF_CLK
VDD
GND
Q2
nc
Q1
VDD
GND
8
7
6
5
R2
33 Zo = 50 Ohm
Q1
VDD
C2
0.1u
LVCMOS
Figure 1. ICS87002-05 Schematic Example
ICS87002BM-05 REVISION B APRIL 16, 2010
7
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