ICS843SDN Datasheet, PDF (8/14 Pages) Integrated Device Technology – FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR

ICS843SDN
FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Schematic Example
Figure 5A shows an example of the ICS843SDN application
schematic. In this example, the device is operated at V_CC = 3.3V.
The 18pF parallel resonant crystal is used. The C1 = 27pF and C2
= 27pF are recommended for frequency accuracy. For a different
board layout, the C1 and C2 values may be slightly adjusted for
optimizing frequency accuracy. Two examples of LVPECL
terminations are shown in this schematic. Additional approaches
are shown in the LVPECL Termination Application Note.
VCC
R1
10 C4
10uF
VCCA
C5
0.01u
XTAL_OUT
XTAL_IN
U1
1
2
VCCA
3
4
VEE
XTAL_OUT
XTAL_IN
VCC
8
7
Q
nQ
nc
6
5
C2
27pF
X1
18pF
25MHz
C1
27pF
VCC
VCC
C3
0.01u
VCC=3.3V
3.3V
R2
R3
133
133
Zo = 50 Ohm
Q
nQ
+
Zo = 50 Ohm
-
R4
R5
82.5
82.5
Zo = 50 Ohm
Zo = 50 Ohm
R6
50
+
-
R7
50
Optional
R8
Y-Termination
50
Figure 5A. ICS843SDN Schematic Example
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
8
ICS843SDNAG REV. A FEBRUARY 19, 2009