ICS843SDN Datasheet, PDF (6/14 Pages) Integrated Device Technology – FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR

ICS843SDN
FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS843SDN
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_CC and V_CCA should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure
1 illustrates this for a generic V_CC pin and also shows that V_CCA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the V_CCA pin.
3.3V
V_CC
.01µF _10Ω
V_CCA
.01µF
10µF
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843SDN has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
X1
18pF Parallel Crystal
XTAL_IN
C1
27p
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843SDNAG REV. A FEBRUARY 19, 2009