ICS843001I-23 Datasheet, PDF (8/24 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER

ICS843001I-23 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Table 6B. AC Characteristics, V_CC = 3.3V ± 5%, V_{CCO_LVCMOS} = V_{CCO_LVPECL} = 2.5V ± 5%, V_EE = 0V, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_OUT
Output Frequency
Q, nQ
REF_OUT
70
19.44
637.5
27
MHz
MHz
t_PD
Propagation Delay; CLK to
NOTE 1
REF_OUT
2.3
2.9
ns
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
622.08MHz,
(12kHz – 20MHz)
1
ps
f_VCO
PLL VCO Lock Range
1.12
t_R / t_F
Output
Rise/Fall Time
Q, nQ
REF_OUT
20% to 80%
20% to 80%
200
350
1.275
700
750
GHz
ps
ps
Q, nQ
46
odc
Output Duty Cycle _{REF_OUT;}
NOTE 3
Using Clock Input
48
54
%
52
%
t_LOCK
PLL Lock Time
60
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the V_CC/2 of the input to V_{CCO_LVCMOS}/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
Table 6C. AC Characteristics, V_CC = V_{CCO_LVCMOS} = V_{CCO_LVPECL} = 2.5V ± 5%, V_EE = 0V, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_OUT
Output Frequency
Q, nQ
REF_OUT
70
19.44
637.5
27
t_PD
Propagation Delay; CLK to
NOTE 1
REF_OUT
2.3
2.9
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
622.08MHz,
(12kHz – 20MHz)
1.1
f_VCO
PLL VCO Lock Range
1.12
t_R / t_F
Output
Rise/Fall Time
Q, nQ
REF_OUT
20% to 80%
20% to 80%
200
350
1.275
700
750
Q, nQ
46
54
odc
Output Duty Cycle _{REF_OUT;}
NOTE 3
Using Clock Input
48
52
t_LOCK
PLL Lock Time
60
Units
MHz
MHz
ns
ps
GHz
ps
ps
%
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the V_CC/2 of the input to V_{CCO_LVCMOS}/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
8
©2011 Integrated Device Technology, Inc.