ICS843001I-23 Datasheet, PDF (16/24 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER

ICS843001I-23 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Schematic Layout
Figure 6 (next page) shows an example of ICS843001I-23 application
schematic. In this example, the device is operated V_CC =
V_{CCO_LVCMOS} = V_{CCO_LVPECL} = 3.3V. The 18pF parallel resonant
17.5-29.54MHz crystal is used. The load capacitance C1 = 22pF and
C2 = 22pF are recommended for frequency accuracy. Depending on
the parasitic of the printed circuit board layout, these values might
require a slight adjustment to optimize the frequency accuracy.
Crystals with other load capacitance specifications can be used. This
will require adjusting C1 and C2. For this device, the crystal load
capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843001I-23 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
16
©2011 Integrated Device Technology, Inc.