9ZXL1550_15 Datasheet, PDF (8/18 Pages) Integrated Device Technology – 15-output DB1900Z Low-Power Derivative

9ZXL1550 DATASHEET
Electrical Characteristics–Skew and Differential Jitter Parameters
TA = T_COM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
CLK_IN, DIF[x:0]
t_{SPO_PLL}
Input-to-Output Skew in PLL mode
nominal value @ 35°C, 3.3V, 100MHz
-150
-117
-50
ps
CLK_IN, DIF[x:0]
t_{PD_BYP}
Input-to-Output Skew in Bypass mode
nominal value @ 35°C, 3.3V
2.5
4
4.5
ns
CLK_IN, DIF[x:0]
t_{DSPO_PLL}
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50
0
50
ps
NOTES
1,2,4,5,8
1,2,3,5,8
1,2,3,5,8
Input-to-Output Skew Varation in Bypass mode
CLK_IN, DIF[x:0]
t_{DSPO_BYP}
across temperature for a given voltage
-250
0
250
ps 1,2,3,5,8
CLK_IN, DIF[x:0]
t_DTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
1
5
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0]
t_DSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
5
75
ps 1,2,3,5,8
DIF[x:0]
Output-to-Output Skew across all outputs
t_{SKEW_ALL (Common to Bypass and PLL mode). 100MHz}
53
75
ps 1,2,3,8
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
Duty Cycle Distortion
j_peak-hibw
j_peak-lobw
pll_HIBW
pll_LOBW
t_DC
t_DCD
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
0
1.8
2.5
dB
7,8
0
0.7
2
dB
7,8
2
3.3
4
MHz
8,9
0.7
1.2
1.4
MHz
8,9
45
50
55
%
1
0
1
2
%
1,10
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
12
50
ps
1,11
0
50
ps
1,11
Notes for preceding table:
1 _{Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.}
2 _{Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.}
3 _{All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.}
4 _{This parameter is deterministic for a given device}
5 _{Measured with scope averaging on to find mean value.}
6. _{t is the period of the input clock}
7 _{Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.}
8. _{Guaranteed by design and characterization, not 100% tested in production.}
9 _{Measured at 3 db down or half power point.}
10 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
11 _{Measured from differential waveform}
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
8
REVISION E 11/20/15