9ZXL1550_15 Datasheet, PDF (6/18 Pages) Integrated Device Technology – 15-output DB1900Z Low-Power Derivative

9ZXL1550 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters
TA = T_COM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
T_COM
V_IH
V_IL
I_IN
Commmercial range
0
35
70
°C
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, V_IN = GND, V_IN = VDD
2
GND - 0.3
-5
V_DD + 0.3 V
0.8
V
5
uA
Input Current
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
V_IN = VDD; Inputs with internal pull-down resistors
200
uA
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
F_ibyp
F_ipll
F_ipll
L_pin
C_IN
C_{INDIF_IN}
C_OUT
T_STAB
V_DD = 3.3 V, Bypass mode
V_DD = 3.3 V, 100MHz PLL mode
V_DD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
33
150
90
100.00 110
120 133.33 147
7
1.5
5
1.5
2.7
6
0.65
1
MHz
2
MHz
2
MHz
2
nH
1
pF
1
pF
1,4
pF
1
ms
2
Input SS Modulation
Frequency
f_MODIN
Allowable Frequency
(Triangular Modulation)
30
31.5
33
kHz
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
t_F
Fall time of control inputs
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_R
V_ILSMB
V_IHSMB
V_OLSMB
I_PULLUP
V_DDSMB
t_RSMB
t_FSMB
f_MINSMB
Rise time of control inputs
@ I_PULLUP
@ V_OL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4_{DIF_IN input}
5_{The differential input clock must be running for the SMBus to be active}
25
300
us
1,3
5
ns
1,2
5
ns
1,2
0.8
V
2.1
V_DDSMB
V
0.4
V
4
mA
2.7
5.5
V
1000
ns
1
300
ns
1
100
kHz
5
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
6
REVISION E 11/20/15