9ZXL1550_15 Datasheet, PDF (2/18 Pages) Integrated Device Technology – 15-output DB1900Z Low-Power Derivative

9ZXL1550 DATASHEET
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 1
48 VDDIO
GNDA 2
47 GND
100M_133M# 3
46 DIF9#
HIBW_BYPM_LOBW# 4
45 DIF9
CKPWRGD_PD# 5
44 DIF8#
GND 6
43 DIF8
VDDR 7
DIF_IN 8
9ZXL1550
42 GND
41 VDD
DIF_IN# 9
SMB_A0_tri 10
EPAD is Pin 65
40 DIF7#
39 DIF7
SMBDAT 11
38 DIF6#
SMBCLK 12
37 DIF6
SMB_A1_tri 13
36 VDDIO
FBOUT_NC# 14
35 GND
FBOUT_NC 15
34 DIF5#
GND 16
33 DIF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9x9 mm 64-pin VFQFPN
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Power Management Table
Inputs
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
Control Bits
SMBus
EN bit
X
0
1
Outputs
DIFx/ FBOUT_NC/
DIFx# FBOUT_NC#
Low/Low Low/Low
Low/Low Running
Running Running
PLL State
OFF
ON
ON
Power Connections
Pin Number
VDD
VDDIO
GND
1
2
7
6
16,20,25,32,
26, 41, 58
19,31,36,48,5
1,63
35,42,47,52,
57,64
Description
Analog PLL
Analog Input
DIF clocks
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
(MHz)
100.00
133.33
DIFx
(MHz)
DIF_IN
DIF_IN
PLL Operating Mode
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
Tri-Level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
2
REVISION E 11/20/15