9SQL4954 Datasheet, PDF (8/20 Pages) Integrated Device Technology – 4-output CK420BQ Derivative

9SQL4954 DATASHEET
EAlrecchtirtieccatluCrehsa₁r_,a₂c_, t₅eristics–Phase Jitter Parameters - PCIe Common Clocked (CC)
T_AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
SPECIFICATION
LIMIT
UNITS
NOTES
Phase Jitter,
PLL Mode
t_jphPCIeG1-CC
t_jphPCIeG2-CC
PCIe Gen 1
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
17
30
0.4
0.6
1.1
1.7
86
ps (p-p) 3
ps
3
(rms)
3.1
ps
(rms)
t_jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.29
0.42
1
ps
(rms)
PCIe Gen 4
t_{jphPCIeG4-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)}
0.29
0.42
0.5
ps
(rms)
Electrical Characteristics–Phase Jitter Parameters - PCIe Independent Reference (IR)
Architectures^{1, 5, 6}
T_AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX INDUSTRY LIMIT UNITS NOTES
Phase Jitter, PLL
Mode
t_jphPCIeG1-
SRIS
t_jphPCIeG2-
SRIS
t_jphPCIeG3-
SRIS
t_jphPCIeG4-
SRIS
PCIe Gen 1
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz, CDR = 10MHz)
n/a
0.8
1.2
0.4
0.5
n/a
None
2
0.7
None
ps
2, 7
(rms)
ps
2
(rms)
ps
2
(rms)
ps
(rms) ^{2, 7}
Notes on PCIe Filter Phase Jitter Tables
1 _{Applies to all differential outputs, guaranteed by design and characterization.}
2 _{Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Additive jitter for RMS values is calculated by solving for b where [b=sqrt(c} 2_-a 2_{)], a is rms input jitter and c is rms total jitter.}
5 _{Driven by 9FGL0841 or equivalent}
6 _{IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock}
architectures.
7 _{According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not}
defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this
table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates
4-OUTPUT CK420BQ DERIVATIVE
8
DECEMBER 12, 2016