9SQL4954 Datasheet, PDF (7/20 Pages) Integrated Device Technology – 4-output CK420BQ Derivative

9SQL4954 DATASHEET
Electrical Characteristics–BCLK Low-Power HCSL Outputs
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Crossing Voltage (abs)
Crossing Voltage (var)
SYMBOL
Trf
Vcross_abs
Δ-Vcross
CONDITIONS
Scope averaging on, fast setting
Scope averaging, slow setting
Scope averaging off
Scope averaging off
MIN
TYP
MAX UNITS NOTES
2.2
3.2
4.5 ^V/ns 2,3
1.5
2.3
3.5 V/ns 2,3
250
411
550 mV 1,4,5
12
140 mV 1,4,9
Avg. Clock Period Accuracy TPERIOD_AVG
-50
0
+2550 ^ppm 2,10,13
Absolute Period
Jitter, Cycle to cycle
Voltage High
TPERIOD_ABS
t_jcyc-cyc
V_HIGH
Voltage Low
V_LOW
Absolute Max Voltage
Vmax
Absolute Min Voltage
Vmin
Duty Cycle
t_DC
Slew rate matching
ΔTrf
Skew, Output to Output
t_sk3
1 _{Measured from single-ended waveform.}
2 _{Measured from differential waveform.}
Includes jitter and Spread Spectrum Modulation 9.94906 10.0 10.1011 ns
2,6
23
50
ps
2
Statistical measurement on single-ended signal ₆₆₀
770
850
1,15
using oscilloscope math function. (Scope
mV
averaging on)
-150
25
150
1,15
Measurement on single ended signal using
absolute value. (Scope averaging off)
822
1150 _mV 1,7,15
-300
-63
1,8,15
45
49
55
%
2
14
20
% 1,14
Averaging on, V_T = 50%
24
50
ps
2
3 _{Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic}
through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
4 _{Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.}
5 _{Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points}
for this measurement.
6 _{Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread}
spectrum modulation.
7 _{Defined as the maximum instantaneous voltage including overshoot.}
8 _{Defined as the minimum instantaneous voltage including undershoot.}
9 _{Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in}
V_CROSS for any particular system.
10 _{Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding PPM considerations.}
11 _{System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.}
Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential
probe can be used for differential measurements. Test load CL = 2 pF.
12 _{TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed}
to droop back into the VRB ±100 mV differential range.
13 _{PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or}
100 Hz. For 50 PPM, then we have an error budget of 100 Hz/PPM * 50 PPM = 5 kHz. The period is to be measured with a frequency counter
with measurement window set to 100 ms or greater. The ±50PPM applies to systems that do not employ Spread Spectrum Clocking, or that
use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal shift in maximum
period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,550 PPM.
14 _{Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the}
median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-;
the maximum allowed difference should not exceed 20% of the slowest edge rate.
15 _{At default SMBus amplitude settings.}
DECEMBER 12, 2016
7
4-OUTPUT CK420BQ DERIVATIVE