9DBV0431 Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – LP-HCSL outputs save 8 resistors; minimal board space and BOM cost

9DBV0431 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on 3.0V/ns setting
Scope averaging on 2.0V/ns setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
2
3.2
4 V/ns 1, 2, 3
1.3 2.3 3.3 V/ns 1, 2, 3
5.4 20 % 1, 2, 4
Voltage High
Voltage Low
V_HIGH
V_LOW
Statistical measurement on single-ended signal _{660 779 850}
1,7
using oscilloscope math function. (Scope
mV
averaging on)
-150 21 150
1,7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
835 1150 _mV
1
absolute value. (Scope averaging off)
-300 -42
1
Vswing
Vswing
Scope averaging off
300 1515
mV 1,2,7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 409 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
14 140 mV 1, 6
1_{Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential}
trace impedance).
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
7 _{At default SMBus settings.}
Electrical Characteristics–Current Consumption
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Operating Supply Current
(PLL Mode)
I_DDROP
I_DDOP
VDDR, @100MHz
VDDA + VDD1.8, @100MHz
Operating Supply Current
(PLL-Bypass Mode)
I_DDROP
I_DDOP
VDDR, @100MHz
VDDA + VDD1.8, @100MHz
Powerdown Current
I_DDRPD
I_DDPD
VDDR, CKPWRGD_PD# = 0
VDDA + VDD1.8, CKPWRGD_PD# = 0
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input clock stopped, and CKPWRGD_PD# pin low.}
4.2
6
27
33
2.2
3
20
25
0.014
0.3
0.95
1.2
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1
1,2
1, 2
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB
8
REVISION C 11/26/14