9DBV0431 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – LP-HCSL outputs save 8 resistors; minimal board space and BOM cost

9DBV0431 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
1.8V Supply Voltage
VDD
Supply voltage for core, analog and LVCMOS
outputs
1.7
1.8
1.9
V
1
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Schmitt Trigger Postive
Going Threshold Voltage
Schmitt Trigger Negative
Going Threshold Voltage
T_COM
T_IND
V_IH
V_IM
V_IL
V_T+
V_T-
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, where indicated
Single-ended inputs, where indicated
0
25
70
°C
1
-40
25
85
°C
1
0.75 V_DD
0.4 V_DD
-0.3
V_DD + 0.3 V
1
0.6 V_DD
V
1
0.25 V_DD V
1
0.4 V_DD
0.7 V_DD
V
1
0.1 V_DD
0.4 V_DD
V
1
Hysteresis Voltage
Output High Voltage
Outputt Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
Input SS Modulation
Frequency
OE# Latency
Tdrive_PD#
V_H
V_IH
V_IL
I_IN
I_INP
F_ibyp
F_ipll100
F_ipll125
F_ipll62
L_pin
C_IN
C_{INDIF_IN}
C_OUT
T_STAB
f_MODIN
t_LATOE#
t_DRVPD
V_T+ - V_T-
Single-ended outputs, except SMBus. I_OH = -2mA
Single-ended outputs, except SMBus. I_OL = -2mA
Single-ended inputs, V_IN = GND, V_IN = VDD
Single-ended inputs
V_IN = 0 V; Inputs with internal pull-up resistors
V_IN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
125MHz PLL mode
50MHz PLL mode
0.1 V_DD
V_DD-0.45
-5
-200
1
50
62.5
25
Logic Inputs, except DIF_IN
1.5
DIF_IN differential clock inputs
1.5
Output pin capacitance
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
30
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
1
DIF output enable after
PD# de-assertion
100
125
50
0.6
31.5
175
0.4 V_DD
V
1
V
1
0.45
V
1
5
uA
1
200
uA
1
200
MHz
2
150
MHz
2
170
MHz
2
70
MHz
2
7
nH
1
5
pF
1
2.7
pF
1,6
6
pF
1
1
ms
1,2
33
kHz
1
3
clocks 1,3
300
us
1,3
Tfall
t_F
Fall time of single-ended control inputs
Trise
t_R
Rise time of single-ended control inputs
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
2.1
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
SMBus Sink Current
I_PULLUP
@ V_OL
4
Nominal Bus Voltage
V_DDSMB
1.7
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
t_FSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
5
ns
1,2
5
ns
1,2
0.8
V
1,4
3.6
V
1,5
0.4
V
1
mA
1
3.6
V
1
1000
ns
1
300
ns
1
SMBus Operating Frequency f_MAXSMB
Maximum SMBus operating frequency
400
kHz 1,7
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VILSMB <= 0.25VDDSMB}
5 _{For VDDSMB < 3.3V, VIHSMB >= 0.7VDDSMB}
6_{DIF_IN input}
7_{The differential input clock must be running for the SMBus to be active}
REVISION C 11/26/14
7
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB