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9DBV0431 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – LP-HCSL outputs save 8 resistors; minimal board space and BOM cost | |||
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4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
9DBV0431
DATASHEET
Description
The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
⢠4 - 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
Key Specifications
⢠DIF cycle-to-cycle jitter <50ps
⢠DIF output-to-output skew <50ps
⢠DIF additive phase jitter is <100fs rms for PCIe Gen3
⢠DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
⢠LP-HCSL outputs save 8 resistors; minimal board space
and BOM cost
⢠53mW typical power consumption in PLL mode; minimal
power consumption
⢠OE# pins; support DIF power management
⢠HCSL compatible differential input; can be driven by
common clock sources
⢠Programmable Slew rate for each output; allows tuning for
various line lengths
⢠Programmable output amplitude; allows tuning for various
application environments
⢠Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
⢠Outputs blocked until PLL is locked; clean system start-up
⢠Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
⢠Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
⢠3.3V tolerant SMBus interface works with legacy controllers
⢠Space saving 32-pin 5x5mm VFQFPN; minimal board
space
⢠Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
OE(3:0)#
CLK_IN
CLK_IN#
SADR_tri
HIBW_BYPM_LOBW#
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
ZDB PLL
4
DIF(3:0)
9DBV0431 REVISION C 11/26/14
1
©2014 Integrated Device Technology, Inc.
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