8T73S1802_17 Datasheet, PDF (8/25 Pages) Integrated Device Technology – 1:2 Clock Fanout Buffer and Frequency Divider

8T73S1802 Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics, V_CC = V_{CCO_QA} = V_{CCO_QB} = 3.0V to 3.465V or 2.5V±5%, T_A = -40°C to 85°C^{1, 2}
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_IN
f_OUT
V_PP
V_CMR
V_O(pp)
Input Frequency CLK
Output
QA
Frequency
QB
Peak-to-Peak Input Voltage³
Common Mode 
Input Voltage^{4, 5}
Single-ended
Output 
Voltage Swing,
QA
Peak-to-Peak
0.15
1.0
1000
1000
200
1.3
V_CC –
V_PP /2
0.5
Units
MHz
MHz
MHz
V
V
V
Differential
V_{DIFF_OUT}
Output 
Voltage Swing,
QA
Peak-to-Peak
1.0
V
t_PD
Propagation
Delay
CLK to QA
CLK to QB
(Any Divider)
(Any Divider)
150
450
700
ps
900
1100
1500
ps
t_DIS
Output Disable Time
EN to Outputs Disabled
(High-Impedance)
15
ns
t_EN
tsk(o)
Output Enable Time
Output Skew^{6, 7} QA to QB
EN to Outputs Enabled
when QA and QB have the same
Output Divider
400
ns
650
1000
ps
tsk(pp)
Part-to-Part
Skew
QA
QB
50
ps
300
ps
tsk(p)
t(odc)
t_R / t_F
Pulse Skew
QA
Output 
QA⁹
Duty Cycle
Distortion⁸
QB
Output 
Rise/Fall Time, QA
Differential
f_IN = 800MHz
f_IN = 200MHz, N = 1
f_IN = 200MHz, N = 2, 4, 8
20% to 80%
100
ps
-50
0
50
ps
-225
225
ps
-150
150
ps
120
350
ps
V/t
Output
Slew Rate
QB
QB
QA
20% to 80%, V_{CCO_QB} = 3.3V
1.4
5
V/ns
20% to 80%, V_{CCO_QB} = 2.5V
1.4
3
V/ns
200MHz – 1GHz,
Integration Range: 12kHz - 20MHz
150
fs
QA
tjit
Additive
Phase Jitter
QB
200MHz – 1GHz,
Integration Range: 50kHz - 40MHz
250MHz,
Integration Range: 12kHz - 20MHz
250
fs
250
fs
QB
250MHz,
Integration Range: 50kHz - 40MHz
400
fs
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 2. QA is terminated 50 to V_T = V_CC - 2V, the QB load is terminated 50 to V_CC/2.
NOTE 3. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-
gle-ended Levels.
NOTE 4. V_IL should not be less than -0.3V. V_IH should not be higher than V_CC.
©2017 Integrated Device Technology, Inc.
8
February 7, 2017