8T73S1802_17 Datasheet, PDF (4/25 Pages) Integrated Device Technology – 1:2 Clock Fanout Buffer and Frequency Divider

Principles Of Operation
8T73S1802 Datasheet
Control Pins
The control input pins SEL0, SEL1 and EN are 3-level inputs with internal 60k resistors that pull the input to the V_CC level when left open.
Each input has three logic states: low (0), mid (V_CC/2) and high (1). Connect a control input to GND for achieving the low (0) state. For
the high (1) state, connect the input to V_CC or leave the input open. For the mid state, connect an external 60k resistor from the input to
GND. See Table 4D for the 3-state input min and max levels.
Operation Modes
The device offers a many combinations of divider values and output enable states. See Table 3 for the supported modes.
Table 3. Operation Modes¹
Input^{2 3 4}
Output Divider
EN
SEL1
SEL0
QA (LVPECL)
QB (LVCMOS)
0
X
X
Disabled
Disabled
0
÷4
÷4
0
MID
÷1
÷1
1
÷2
÷2
MID
MID
÷8
÷1
MID
1
÷1
÷2
1
0
÷4
÷8
0
÷1
÷4
0
1
÷2
÷4
1
0
÷8
÷4
1
1
Disable
÷4
NOTE 1. In the default state (control input left open), QA is disabled and QB = ÷4.
NOTE 2. 0 = Low, MID = V_CC/2, 1 = High; X = either 0, MID or 1.
NOTE 3. 0 = Low, MID = V_CC/2, 1 = High; X = either 0, MID or 1.
NOTE 4. Unspecified EN, SEL1, SEL0 input logic states are reserved and should not be used.
©2017 Integrated Device Technology, Inc.
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February 7, 2017