8T49N286_16 Datasheet, PDF (8/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N286 Datasheet
Input Clock Monitor
Each clock input is monitored for Loss of Signal (LOS). If no activity
has been detected on the clock input within a user-selectable time
period then the clock input is considered to be failed and an internal
Loss-of-Signal status flag is set, which may cause an input
switchover depending on other settings. The user-selectable time
period has sufficient range to allow a gapped clock missing many
consecutive edges to be considered a valid input.
User-selection of the clock monitor time-period is based on a counter
driven by a monitor clock. The monitor clock is fixed at the frequency
of PLL0’s VCO divided by 8. With a VCO range of 3GHz - 4GHz, the
monitor clock has a frequency range of 375MHz to 500MHz.
The monitor logic for each input reference will count the number of
monitor clock edges indicated in the appropriate Monitor Control
register. If an edge is received on the input reference being
monitored, then the count resets and begins again. If the target edge
count is reached before an input reference edge is received, then an
internal soft alarm is raised and the count re-starts. During the soft
alarm period, the PLL(s) tracking this input will not be adjusted. If an
input reference edge is received before the count expires for the
second time, then the soft alarm status is cleared and the PLL(s) will
resume adjustments. If the count expires again without any input
reference edge being received, then a Loss-of-Signal alarm is
declared.
It is expected that for normal (non-gapped) clock operation, users will
set the monitor clock count for each input reference to be slightly
longer than the nominal period of that input reference. A margin of
2-3 monitor clock periods should give a reasonably quick reaction
time and yet prevent false alarms.
For gapped clock operation, the user will set the monitor clock count
to a few monitor clock periods longer than the longest expected clock
gap period. The monitor count registers support 17-bit count values,
which will support at least a gap length of two clock periods for any
supported input reference frequency, with longer gaps being
supported for faster input reference frequencies. Since gapped
clocks usually occur on input reference frequencies above 100MHz,
gap lengths of thousands of periods can be supported.
Using this configuration for a gapped clock, the PLL will continue to
adjust while the normally expected gap is present, but will freeze
once the expected gap length has been exceeded and alarm after
twice the normal gap length has passed.
Once a LOS on any of the input clocks is detected, the appropriate
internal LOS alarm will be asserted and it will remain asserted until
that input clock returns and will be validated by the receipt of 8 rising
clock edges on that input reference. If another error condition on the
same input clock is detected during the validation time then the alarm
remains asserted and the validation time starts over.
Each LOS flag may also be reflected on one of the GPIO[7:0]
outputs. Changes in status of any reference can also generate an
interrupt if not masked.
Holdover
8T49N286 supports a small initial holdover frequency offset for each
PLL path in non-gapped clock mode. When the input clock monitor is
set to support gapped clock operation, this initial holdover frequency
offset is indeterminate since the desired behavior with gapped clocks
is for the PLL to continue to adjust itself even if clock edges are
missing. In gapped clock mode, the PLL will not enter holdover until
the input is missing for at least 2 LOS monitor periods.
The holdover performance characteristics of a clock are referred as
its accuracy and stability, and are characterized in terms of the
fractional frequency offset. The 8T49N286 can only control the initial
frequency accuracy. Longer-term accuracy and stability are
determined by the accuracy and stability of the external oscillator.
When a PLL loses all valid input references, it will enter the holdover
state. In fast average mode, the PLL will initially maintain its most
recent frequency offset setting and then transition at a rate dictated
by its selected phase-slope limit setting to a frequency offset setting
that is based on historical settings. This behavior is intended to
compensate for any frequency drift that may have occurred on the
input reference before it was detected to be lost.
The historical holdover value will have three options:
• Return to center of tuning range within the V_CO band
• Instantaneous mode - the holdover frequency will use the
DPLL current frequency 100msec before it entered holdover.
The accuracy is shown in Table 12, AC Characteristics Table.
• Fast average mode - an internal IIR (Infinite Impulse
Response) filter is employed to get the frequency offset. The
IIR filter gives a 3dB attenuation point corresponding to a
nominal period of 20 minutes. The accuracy is shown in Table
12, AC Characteristics Table.
When entering holdover, each PLL will set a separate internal HOLD
alarm internally. This alarm may be read from internal status register,
appear on the appropriate GPIO pin and/or assert the nINT output.
While a PLL is in holdover, its frequency offset is now relative to the
crystal input and so the output clocks derived from that PLL will be
tracing their accuracy to the local oscillator or crystal. At some point
in time, depending on the stability & accuracy of that source, the
clock(s) derived from that PLL will have drifted outside of the limits of
the holdover state and the system will be considered to be in a
free-run state. Since this borderline is defined outside the PLL and
dictated by the accuracy and stability of the external local crystal or
oscillator, the 8T49N286 cannot know or influence when that
transition occurs. As a result, the 8T49N286 will remain in the
holdover state internally.
©2016 Integrated Device Technology, Inc.
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Revision 7, October 27, 2016