8T49N286_16 Datasheet, PDF (26/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N286 Datasheet
Bit Field Name
PRI1_1[1:0]
PRI1_2[1:0]
PRI1_3[1:0]
REFDIS1_0
REFDIS1_1
REFDIS1_2
REFDIS1_3
STATE1[1:0]
PRE1_0[20:0]
PRE1_1[20:0]
PRE1_2[20:0]
PRE1_3[20:0]
Rsvd
Field Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Digital PLL1 Input Control Register Block Field Descriptions
Default Value
01b
10b
11b
Description
Switchover priority for Input Reference 1 when used by Digital PLL1:
00 = 1st priority
01 = 2nd priority
10 = 3rd priority
11 = 4th priority
Switchover priority for Input Reference 2 when used by Digital PLL1:
00 = 1st priority
01 = 2nd priority
10 = 3rd priority
11 = 4th priority
Switchover priority for Input Reference 3 when used by Digital PLL1:
00 = 1st priority
01 = 2nd priority
10 = 3rd priority
11 = 4th priority
Input Reference 0 Switching Selection Disable for Digital PLL1:
0b
0 = Input Reference 0 is included in the switchover sequence for Digital PLL1
1 = Input Reference 0 is not included in the switchover sequence for Digital PLL1
Input Reference 1 Switching Selection Disable for Digital PLL1:
0b
0 = Input Reference 1 is included in the switchover sequence for Digital PLL1
1 = Input Reference 1 is not included in the switchover sequence for Digital PLL1
Input Reference 2 Switching Selection Disable for Digital PLL1:
0b
0 = Input Reference 2 is included in the switchover sequence for Digital PLL1
1 = Input Reference 2 is not included in the switchover sequence for Digital PLL1
Input Reference 3 Switching Selection Disable for Digital PLL1:
0b
0 = Input Reference 3 is included in the switchover sequence for Digital PLL1
1 = Input Reference 3 is not included in the switchover sequence for Digital PLL1
Digital PLL1 State Machine Control:
00 = Run automatically
00b
01 = Force FREERUN state - set this if in Synthesizer Mode for PLL1
10 = Force NORMAL state
11 = Force HOLDOVER state
000000h Pre-divider ratio for Input Reference 0 when used by Digital PLL1.
000000h
000000h
Pre-divider ratio for Input Reference 1 when used by Digital PLL1.
Pre-divider ratio for Input Reference 2 when used by Digital PLL1.
000000h Pre-divider ratio for Input Reference 3 when used by Digital PLL1.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
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Revision 7, October 27, 2016