8T49N286_16 Datasheet, PDF (32/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N286 Datasheet
Bit Field Name
GPO6SEL[2:0]
GPO7SEL[2:0]
GPO[7:0]
Rsvd
Field Type
R/W
R/W
R/W
R/W
GPIO Control Register Block Field Descriptions
Default Value
000b
Description
Function of GPIO[6] pin when set to output mode by GPIO_DIR[6] register bit:
000 = General Purpose Output (value in GPO[6] register bit driven on GPIO[6] pin
001 = Loss-of-Signal Status Flag for Input Reference 2 reflected on GPIO[6] pin
010 through 111 = reserved
000b
Function of GPIO[7] pin when set to output mode by GPIO_DIR[7] register bit:
000 = General Purpose Output (value in GPO[7] register bit driven on GPIO[7] pin
001 = Loss-of-Signal Status Flag for Input Reference 3 reflected on GPIO[7] pin
010 through 111 = reserved
00h
Output Values reflect on pin GPIO[7:0] when General-Purpose Output Mode selected.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 7J. Output Driver Control Register Bit Field Locations and Descriptions
Output Driver Control Register Block Field Locations
Address (Hex)
0077
0078
0079
007A
007B
007C
D7
D6
D5
OUTMODE7[2:0]
OUTMODE5[2:0]
OUTMODE3[2:0]
OUTMODE1[2:0]
D4
D3
D2
D1
OUTEN[7:0]
POL_Q[7:0]
SE_MODE7
OUTMODE6[2:0]
SE_MODE5
OUTMODE4[2:0]
SE_MODE3
OUTMODE2[2:0]
SE_MODE1
OUTMODE0[2:0]
D0
SE_MODE6
SE_MODE4
SE_MODE2
SE_MODE0
Bit Field Name Field Type
OUTEN[7:0]
R/W
POL_Q[7:0]
R/W
OUTMODEm
[2:0]
R/W
SE_MODEm
R/W
Output Driver Control Register Block Field Descriptions
Default Value Description
Output Enable control for Clock Outputs Q[7:0], nQ[7:0]:
00h
0 = Qn is in a high-impedance state
1 = Qn is enabled as indicated in appropriate OUTMODEn[2:0] register field
Polarity of Clock Outputs Q[7:0], nQ[7:0]:
00h
0 = normal polarity
1 = inverted polarity
001b
Output Driver Mode of Operation for Clock Output Pair Qm, nQm:
000 = High-impedance
001 = LVPECL
010 = LVDS
011 = LVCMOS
100 = HCSL
101 - 111 = reserved
Behavior of Output Pair Qm, nQm when LVCMOS operation is selected
0b
(Must be 0 if LVDS, HCSL or LVPECL output style is selected):
0 = Qm and nQm are both the same frequency but inverted in phase
1 = Qm and nQm are both the same frequency and phase
©2016 Integrated Device Technology, Inc.
32
Revision 7, October 27, 2016