840N022 Datasheet, PDF (8/13 Pages) Integrated Device Technology – FemtoClock® NG Crystal-to-LVCMOS/LVTTL Clock

840N022 DATA SHEET
Schematic Example
Figure 2 shows an example 840N022 application schematic in which
the device is operated at V_DD = +3.3V. The schematic example focus-
es on functional connections and is intended as an example only and
may not represent the exact user configuration. Refer to the pin de-
scription and functional tables in the datasheet to ensure the logic
control inputs are properly set. For example OE and FREQ_SEL can
be configured from an FPGA instead of set with pull- up and pulldown
resistors as shown
The crystal is to be laid out on the 840N022 side of the board and
close to XTAL_IN and XTAL_OUT pins. Tuning capacitors C1 and C2
can be fine tuned to center the oscillator center frequency.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter perfor-
mance isolation of the V_DD pin from power supply is required. In order
to achieve the best possible filtering, it is recommended that the
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1µF
capacitors on the V_DD and V_DDA pins must be placed on the device
side with direct return to the ground plane though vias. The remaining
filter components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at ap-
proximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is recom-
mended that component values be adjusted and if required, addition-
al filtering be added. Additionally, good general design practices for
power plane voltage stability suggests adding bulk capacitance in the
local area of all devices.
Logic Control Input Examples
for OE and FREQ_SEL
VC C
Set Logic
Input to '1'
VCC
Set Logic
Input to '0'
RU1
1K
To Logic
Input
pins
RD1
Not I nstall
R U2
N ot Inst all
To Logic
Input
pins
R D2
1K
VDD
C4
10uF
VDD A
3. 3V
F B1
2
1
R 1 10
BLM18BB221SN 1
C5
0.1uF
C7
10uF
VDD
C6
0. 1uF
Pla ce o ne 0 .1uF byp ass cap
dir ectl y ad jace nt t o th e VDD
pin and one dir ectl y ad jacen t
to the VDDA pin .
VD DA
C3
U3
0. 1uF
OE
F REQ_SEL
2
5 ^OE
F REQ_SEL
3
XTAL_OUT
7
Q
25MHz (12pf )
4
XTAL_IN
X1
C1
C2
5pF
5pF
R3
Zo = 50 Ohm
33
LVCMOS Receiv er
Figure 2. 840N022 Schematic Example
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
8
SYNTHESIZER
REVISION A 8/14/15