840N021 Datasheet, PDF (8/13 Pages) Integrated Device Technology – FemtoClock NG Crystal-to-LVCMOS/LVTTL Clock

840N021 DATA SHEET
Schematic Example
Figure 2 shows an example 840N021 application schematic in which
the device is operated at V_DD = V_DDA = +3.3V. The schematic
example focuses on functional connections and is intended as an
example only and may not represent the exact user configuration.
Refer to the pin description and functional tables in the datasheet to
ensure the logic control inputs are properly set. For example OE can
be configured from an FPGA instead of set with pull up and pull down
resistors as shown.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter
performance isolation of the V_DD pin from power supply is required.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1μF capacitor on the V_DD pin must be placed on the device side
with direct return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
Figure 2. 840N021 Schematic Layout
REVISION A 8/14/15
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FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
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